What Happens To The Bits In A Shift Register

Digital Circuits - Shift Registers

We know that one flip-flop tin can shop one-fleck of information. In order to store multiple bits of information, we require multiple flip-flops. The group of flip-flops, which are used to concur (shop) the binary data is known as annals.

If the register is capable of shifting bits either towards right hand side or towards left hand side is known as shift register. An 'N' bit shift register contains 'Northward' flip-flops. Post-obit are the four types of shift registers based on applying inputs and accessing of outputs.

Serial In − Series Out shift annals
Serial In − Parallel Out shift register
Parallel In − Series Out shift register
Parallel In − Parallel Out shift register

Serial In − Serial Out (SISO) Shift Register

The shift register, which allows series input and produces serial output is known equally Serial In – Series Out (SISO) shift annals. The block diagram of iii-chip SISO shift register is shown in the post-obit figure.

SISO

This block diagram consists of 3 D flip-flops, which are cascaded. That means, output of one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the same clock signal is applied to each 1.

In this shift register, we can send the bits serially from the input of left nearly D flip-bomb. Hence, this input is too called as serial input. For every positive border triggering of clock signal, the data shifts from one stage to the next. So, nosotros can receive the bits serially from the output of right most D flip-bomb. Hence, this output is also chosen as serial output.

Example

Let us meet the working of 3-bit SISO shift register by sending the binary information "011" from LSB to MSB serially at the input.

Assume, initial condition of the D flip-flops from leftmost to rightmost is $Q_{2}Q_{i}Q_{0}=000$. We can sympathise the working of 3-bit SISO shift register from the following table.

No of positive edge of Clock	Serial Input	Q₂	Q_ane	Q₀
0	-	0	0	0
1	1(LSB)	1	0	0
2	1	1	ane	0
3	0(MSB)	0	1	1(LSB)
4	-	-	0	1
five	-	-	-	0(MSB)

The initial status of the D flip-flops in the absence of clock signal is $Q_{two}Q_{1}Q_{0}=000$. Hither, the series output is coming from $Q_{0}$. And then, the LSB (1) is received at three^rd positive border of clock and the MSB (0) is received at 5^th positive edge of clock.

Therefore, the 3-flake SISO shift register requires 5 clock pulses in order to produce the valid output. Similarly, the Northward-scrap SISO shift annals requires 2N-1 clock pulses in order to shift 'Due north' bit data.

Serial In - Parallel Out (SIPO) Shift Register

The shift register, which allows series input and produces parallel output is known equally Serial In – Parallel Out (SIPO) shift register. The block diagram of 3-chip SIPO shift annals is shown in the following figure.

SIPO

This excursion consists of 3 D flip-flops, which are cascaded. That ways, output of one D flip-flop is continued as the input of side by side D flip-flop. All these flip-flops are synchronous with each other since, the aforementioned clock signal is practical to each one.

In this shift register, we can send the $.25 serially from the input of left almost D flip-flop. Hence, this input is also called as serial input. For every positive border triggering of clock signal, the data shifts from one stage to the adjacent. In this case, we tin can access the outputs of each D flip-flop in parallel. So, we will get parallel outputs from this shift register.

Instance

Allow united states of america run into the working of 3-chip SIPO shift register past sending the binary information "011" from LSB to MSB serially at the input.

Assume, initial condition of the D flip-flops from leftmost to rightmost is $Q_{two}Q_{1}Q_{0}=000$. Here, $Q_{two}$ & $Q_{0}$ are MSB & LSB respectively. Nosotros can empathise the working of three-bit SIPO shift annals from the following tabular array.

No of positive edge of Clock	Serial Input	Q_ii(MSB)	Q_ane	Q₀(LSB)
0	-	0	0	0
1	1(LSB)	one	0	0
2	ane	i	1	0
3	0(MSB)	0	1	ane

The initial status of the D flip-flops in the absence of clock bespeak is $Q_{2}Q_{1}Q_{0}=000$. The binary information "011" is obtained in parallel at the outputs of D flip-flops for 3rd positive border of clock.

So, the 3-bit SIPO shift register requires three clock pulses in gild to produce the valid output. Similarly, the N-bit SIPO shift annals requires N clock pulses in order to shift 'Due north' fleck information.

Parallel In − Serial Out (PISO) Shift Annals

The shift register, which allows parallel input and produces serial output is known as Parallel In − Serial Out (PISO) shift register. The block diagram of 3-bit PISO shift register is shown in the following figure.

PISO

This circuit consists of three D flip-flops, which are cascaded. That ways, output of ane D flip-flop is connected as the input of side by side D flip-bomb. All these flip-flops are synchronous with each other since, the same clock indicate is applied to each ane.

In this shift register, we tin can use the parallel inputs to each D flip-flop by making Preset Enable to 1. For every positive edge triggering of clock betoken, the data shifts from one stage to the side by side. So, we will get the serial output from the right most D flip-flop.

Example

Allow us see the working of three-bit PISO shift register by applying the binary information "011" in parallel through preset inputs.

Since the preset inputs are applied earlier positive border of Clock, the initial status of the D flip-flops from leftmost to rightmost will exist $Q_{ii}Q_{1}Q_{0}=011$. We can understand the working of 3-bit PISO shift register from the following table.

No of positive edge of Clock	Q₂	Q_i	Q₀
0	0	1	1(LSB)
1	-	0	1
2	-	-	0(LSB)

Hither, the serial output is coming from $Q_{0}$. And then, the LSB (1) is received before applying positive edge of clock and the MSB (0) is received at 2^nd positive edge of clock.

Therefore, the 3-bit PISO shift register requires two clock pulses in club to produce the valid output. Similarly, the Northward-scrap PISO shift register requires North-ane clock pulses in order to shift 'N' bit data.

Parallel In - Parallel Out (PIPO) Shift Register

The shift register, which allows parallel input and produces parallel output is known as Parallel In − Parallel Out (PIPO) shift register. The block diagram of 3-bit PIPO shift register is shown in the following figure.

PIPO

This circuit consists of three D flip-flops, which are cascaded. That means, output of 1 D flip-flop is continued as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the same clock signal is practical to each one.

In this shift annals, we can utilize the parallel inputs to each D flip-bomb by making Preset Enable to one. We can apply the parallel inputs through preset or clear. These two are asynchronous inputs. That means, the flip-flops produce the corresponding outputs, based on the values of asynchronous inputs. In this case, the effect of outputs is contained of clock transition. So, nosotros will get the parallel outputs from each D flip-bomb.

Example

Allow us see the working of 3-chip PIPO shift annals by applying the binary information "011" in parallel through preset inputs.

Since the preset inputs are applied before positive edge of Clock, the initial status of the D flip-flops from leftmost to rightmost will be $Q_{ii}Q_{1}Q_{0}=011$. And then, the binary information "011" is obtained in parallel at the outputs of D flip-flops earlier applying positive edge of clock.

Therefore, the iii-bit PIPO shift register requires aught clock pulses in society to produce the valid output. Similarly, the N-bit PIPO shift register doesn't crave whatever clock pulse in order to shift 'Northward' bit information.